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CXA3271GE
Fingerprint Sensor
Description The CXA3271GE is an electrostatic capacitance method fingerprint sensor. This monolithic IC integrates the sensor block, sense amplifier (3-bit gain adjustment), sample-and-hold, output amplifier and output buffer needed to acquire fingerprint images, as well as the timing generator for determining the operation of these functions onto a single chip. 30 pin LLGA
Features * Electrostatic capacitance type sensor (charge transfer method) * Number of pixels: 192 x 128 * 317 DPI * Low power consumption (50mW or less) * Single 3.3V power supply * Sensor gain control: 3 bits * S/N ratio improved by on-chip sensor block parasitic capacitance cancel function Applications Fingerprint verification units Structure Silicon gate CMOS IC Absolute Maximum Ratings * Supply voltage * Input voltage * Output voltage * Operating temperature * Storage temperature * Allowable power dissipation
VDD VI VO Topr Tstg PD
VSS - 0.5 to +7.0 V VSS - 0.5 to VDD + 0.5 V VSS - 0.5 to VDD + 0.5 V -20 to +75 C -25 to +125 C 970 mW
Operating Conditions * Supply voltage * Recommended operating temperature
3.15 to 3.45 0 to +50
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E00235-PS
CXA3271GE
Block Diagram
C_SP
UC UC Column Shift Register UC ........ 128 ......... XSP (D/I) Timing Generator SENSOR C_CLK
128
CLK (D/I)
UC ADCLK (D/O) UC UC UC UC UC ........... 192 ........... UC UC UC UC 192 S_CNT Sense AMP (x192) 192 Load S/H & SW (x192) 192 R_SP Row Shift Register
3bit DAC
3 DI (D/I)
Output Buffer AOUT (A/O)
R_CLK
VOS (Bias)
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CXA3271GE
Detailed Block Diagram
Pin Symbol BIAS_O VCS_O 28
BUF
LAND No. 7C 7D 7E 7F 6B 6C 6D 6E 6F 5B 5C 5D 5E 5F 4F 4E 4D 4C 4B 3F 3E 3D 3C 3B 2F 2E 2D 2C
AVDD (P/S) AVSS (P/S) AOUT (A/O) VCS_O (Bias) VOS (Bias) VH (Bias) VM (Bias) VL (Bias) VCS_S (Bias) DVDD (P/S) DVSS (P/S) DVSS (P/S) CSRO (D/O) RSRO (D/O) ADCLK (D/O) C_CK (D/O) C_CLK (D/I) CLK (D/I) HD (D/I) XSP (D/I) DI2 (D/I) DI1 (D/I) DI0 (D/I) MODE (D/I) TEST2 (D/I) TEST1 (D/I) AVSS (P/S) AVDD (P/S)
OAMP
27 26 25
VOS C_CLK
24 C_COUT SR 23 22 21 UC UC UC ..................... 192 .................. UC UC UC OUT UC UC VH VM VL 20 19 18 IN_N (1 to 192) S (1 to 5) N S (1 to 5) SAMP (192) VH VM SC (1 to 192) SC (1 to 192) N VL SC (1 to 192) N C_CO 17 16 15 R_LOG 14 13 12 CLK 11 10 9 8 7 6 D (1 to 192)
C_SP SRN (1 to 128) PG (1 to 128) UC UC UC UC UC UC
C_LOG 128
........ 128 .........
UC UC UC ........... 192 (Dummy) ...........
SENSOR (UC)
192
192 192
SC (1 to 192) DCLK
TG
5
S (1 to 5) N S (1 to 5) DCLK
XSP
XSP MODE HD C_CLK C_CK
5
C_SP
5 4
DA AMP OUT IN
DA AMP OUT
DA AMP OUT IN
DA AMP OUT IN
3 2 1
DSELN
IN
XSP
VDS
D1 (D to 2) VS (3 to 8) VS (1 to 8) N
VS (1 to 8) N VS (3 to 8)
BIAS_SA
VM
VH
VL
VCS_O
TEST1/2
DEC
6
8
2
3
DA
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CXA3271GE
Pin Description Serial Land No. Symbol No. 2B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 19 18 17 16 15 24 23 22 21 20 2C 2D 2E 2F 3B 3C 3D 3E 3F 4B 4C 4D 4E 4F 5B 5C 5D 5E 5F 6B 6C 6D 6E 6F 7B 28 27 26 25 7C 7D 7E 7F SUB AVDD AVSS TEST1 TEST2 MODE DI0 DI1 DI2 XSP HD CLK C_CLK C_CK ADCLK DVDD DVSS DVSS CSRO RSRO VOS VH VM VL VCS_S SUB AVDD AVSS AOUT VCS_O I/O Power Power Power D/I D/I D/I D/I D/I D/I D/I D/I D/I D/I D/O D/O Power Power Power D/O D/O A/O A/O A/O A/O A/O Power Power Power A/O A/O Description Substrate electrode (chip rear surface electrode) 3.3V. Analog power supply 3.3V. Analog GND. Test mode selection. Connect to GND. Test mode selection. Connect to GND. Connect to GND. Gain setting input. (LSB) Gain setting input. Gain setting input. (MSB) Sense start pulse input (negative pulse). The column and row shift registers and the timing generator are cleared by this signal. Connect to GND. Main clock. (1 to 2MHz) Column shift register clock. Connect to C_CK (4E). Column shift register clock output. Connect to C_CLK (4D). Outputs the internally delayed input clock. Digital power supply 3.3V. Digital GND. Digital GND. Column shift register final output. (Connection is not required.) Row shift register final output. (Connection is not required.) Output amplifier reference voltage monitor. (1.65V) Sensor charge voltage monitor. (1 LSB = 80mV) Adjustable within the range of 1.92 to 2.48V by the three bits DI[0:2]. Sense amplifier reference voltage monitor. (1.85V) Dummy cell charge voltage monitor for canceling parasitic capacitance. VL = 2VM - VH Sense amplifier current source bias monitor. (Do not connect.) Substrate electrode (chip rear surface electrode) 3.3V. Analog power supply 3.3V. Analog GND. Sensor output. Output amplifier and output buffer current source bias monitor. (Do not connect.) -4-
CXA3271GE
Electrical Characteristics 1. DC Characteristics Item Analog supply voltage Digital supply voltage Input voltage (High) Input voltage (Low) Output voltage (High) CMOS Output voltage (Low) CMOS Input leak current Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Current consumption 2. AC Characteristics Item Clock input period Output rise delay time Output fall delay time Number of sensor defects Output voltage Air Level AOUT 1 2 600 200 CLK C_CK, ADCLK, RSRO, CSRO C_CK, ADCLK, RSRO, CSRO Applicable pins Symbol AVDD DVDD VIH VIL VIH VIL IL VH VH VL VL VM VOS IDD CMOS input cell CMOS input cell VDD = 3.3V, IOH = -800A VDD = 3.3V, IOL = 2.4mA CMOS input pin VDD = 3.3V (D0 D1 D2) = (L L L) VDD = 3.3V (D0 D1 D2) = (H H H) VDD = 3.3V (D0 D1 D2) = (L L L) VDD = 3.3V (D0 D1 D2) = (H H H) VDD = 3.3V (D0 D1 D2) = ( ) VDD = 3.3V (D0 D1 D2) = ( ) VDD = 3.3V 1.75 1.55 4 Conditions Min. 3.15 3.15 0.7VDD Vss 2.8 0 -5 1.92 2.48 1.76 1.2 1.84 1.65 10 1.92 1.75 14 (Topr = 25C, Vss = 0V) Typ. 3.3 3.3 Max. 3.45 3.45 VDD 0.3VDD 3.3 0.4 5 Unit V V V V V V A V V V V V V mA
(Topr = 25C, Vss = 3.3V) Symbol Conditions Min. Typ. Max. 400 Unit ns 160 200 5 1300 ns ns Sensors mV mV
tpr tpf
CL = 30pF CL = 30pF
Output voltage Water Level AOUT Timing Definition
VDD CLK 0V VDD 0V Output tpr VDD 0V tpf
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CXA3271GE
1 Output voltage Air Level means the output level in the condition where nothing is placed against the sensor surface (in other words, in air). This rating value is obtained by measuring 32 points within one line of the sensor output and then taking the average. The gain setting for this measurement is (011). 2 Output voltage Water Level specifies the degree to which the output level changes from the Air Level when a drop of water is placed on the sensor surface. However, it is unrealistic to place a drop of water on each sensor surface when sorting products, so 32 virtual capacitors (parasitic capacitance equal to the level when a drop of water is placed on the surface) are built into the sensor chip, and the average of these output values is calculated. The difference from the Air Level noted above becomes the Water Level. The gain setting for this measurement is (011).
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CXA3271GE
Electrical Characteristics Measurement Circuit
Digital input pin Digital output pin Analog output pin
AVSS 27 VCS_O/O VH/O 0.1F VL/O 0.1F DVDD 0.1F DVSS RSRO/O 15 C_CK/O 13 CLK/I 11 XSP/I 9 DI1/I 7 MODE/I 5 TEST1/I AVDD 1.0F Vcc 3.3V 3 1 6 4 2 8 10 12 14 16 25 23 21 19 17 28 26 24 22 20 18
AVDD 1.0F AOUT/O VOS/O VM/O 0.1F VCS_S/O DVSS CSRO/O ADCLK/O S1 C_CLK/I HD/I DI2/I DI0/I TEST2/I AVSS
30pF or more is added to each pin.
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CXA3271GE
Application Circuit
Microcomputer During registration
Flash Registered data
DRAM
Fingerprint sensor chip
During verification ASIC Binary value, verification
8-bit A/D
Verification results
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXA3271GE
Description of Operation * Fingerprint sensor principle The principle of this newly developed fingerprint sensor is described below. (Fig. 1) The sensor block contains an array of metal electrodes which are covered on top by an insulating film (over coat). When a finger (which is conductive matter) is placed directly against this surface, the three elements of the metal electrode, the insulating film and the finger form a capacitor. The difference between the fingerprint ridges and valleys is the difference in distance to the metal electrodes, and becomes the difference in the capacitance values of the individually formed capacitors. (The ridge capacitance values are determined by the dielectric constant of the insulating film, but the valleys contain air in addition to this, making the difference between the ridge and valley capacitance values even greater than the difference in distance.) Using this principle, by applying a constant voltage to all metal electrodes, the charge level accumulated in each electrode differs, making it possible to output the unevenness of the fingerprint as an electric signal by transferring and converting these charges to voltages.
, ,
Ridge Valley Fingerprint unevenness Over coat Metal electrode Inter-layer film Si
Fig. 1
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CXA3271GE
S4 Cf1
S6 Cf2 Buf Voo S7
Cs Vcel Cp
Sr
Voi Vsl S3 Vsns S_Amp S11 S2 S1 Ch1 O_Amp VOS S5 Sc
Aout Ch2
Vdmy Cp'
VL Sensor block (192 x 128)
VM VH Sense amplifier block (192) Output block (1)
Fig. 2 * Fingerprint sensor operation (Fig. 2) Description of characters Cs: Capacitance formed between the finger and the metal electrode Cp: Parasitic capacitance formed between the metal electrode and the silicon substrate Cp': Capacitance for canceling Cp (Cp Cp') Ch: Hold capacitance Cf: Feedback capacitance for determining the gain S: Switch V: Node voltage VH - VM VM - VL * Detailed description of operation (All switches are off in the default status.) 1. S1, S4, Sr and S11 are turned on, Vcel is set to voltage VH, and Vdmy is set to voltage VL. Vcel accumulated charge (Cs + Cp) VH Vdmy accumulated charge Cp' VL 2. S1, Sr and S11 are turned off. 3. S2 is turned on and Vsl is set to VM. 4. S4 is turned off. 5. Sr, S3 and S5 are turned on. At this time, the charge level that moves from Vcel and Vdmy to Vsl (actually between capacitances) is: (Cs + Cp) (VH - VM) - Cp' (VM - VL) Cs (VH - VM) This means that the sense amplifier gain is determined independently of the parasitic capacitance, making it possible to obtain the required large signal dynamic range. Vsns = VM - Cs (VH - VM)/Cf1 The voltage Vsns determined as shown above is accumulated in Ch1. 6. S5 is turned off. 7. S6 is turned on and the Voi voltage is set to VOS. 8. S6 is turned off. 9. Sc and S7 are turned on. At this time, the charge level that moves from Ch1 to Cf2 is: (VOS - Vsns) Ch1 This determines the Voo voltage which is accumulated in Ch2 and output to Aout via the buffer. - 10 -
CXA3271GE
Appearance and Readout Order
15.36mm
Cell (1, 1) 10.24mm Cell (128, 1) Sensor Area 192 x 128
Cell (1, 192)
Scan Formation Cell (1, 1) to Cell (1, 192)
16.8mm Cell (128, 192) Cell (128, 1) to Cell (128, 192)
19.8mm
G
Flip
F
E
D
C
B
A 1 2 3 4 5 6 7 8
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CXA3271GE
Notes on Operation
S4 Cf1
S6 Cf2 Buf Voo S7
Cs Vcel Cp
Sr
Voi Vsl S3 Vsns S_Amp S11 S2 S1 Ch1 O_Amp VOS S5 Sc
Aout Ch2
Vdmy Cp'
VL
VM VH
* Aout output variance Aout output variance can be broadly classified into two types. The first is variance intrinsic to the IC, and the second is variance caused by the influence of external noise due to the extremely high sensitivity. * Variance intrinsic to the IC 1. The Aout output DC level fluctuates widely due to the IC. This is caused by the Cp and Cp' capacitance values, the VM voltage level, the voltage differences VH - VM and VM - VL, and the Vos voltage level in the figure above. Vos, VH, VM and VL appear externally as pins. The Aout output level can be set to the desired potential by applying the Vos voltage from an external source. The Aout dynamic range is approximately 0.7 to 2.1V, so checking this output level and externally applying the Vos voltage to set the optimum level is recommended. 2. 192 variances within one line One line is comprised of 192 sensors. Each sensor is connected to a separate S_Amp, so the S_Amp offset appears in the output. (approximately 100 to 200mV) 3. The DC level of a line changes with a certain regularity for some ICs. This is also caused by the S_Amp DC offset. * Variance due to the influence of external noise 1. Output fluctuation due to cross talk from the power supply Power supply fluctuation has a large influence on the Aout output of this IC. In addition to the capacitances between the power supply and GND (approximately 1F, both sides if possible), attaching capacitances of approximately 0.1F to Vos, VH, VM and VL is recommended. 2. Finger stabilization The human body acts as an antenna, so the finger potential changes during the sensing period, producing noise in the Aout output. To prevent this, the potential of the area around the finger being sensed must be equalized with the sensor GND. Measures such as placing a metal plate connected to GND around the sensor so that the finger touches this place during sensing are recommended.
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CXA3271GE
Fingerprint sensors have the silicon chip directly exposed, so care should be taken for the following points. In addition, a cover should be attached to protect the sensor surface during operation. Sensor surface electrostatic strength Contact discharge (150pF, 330): 1.25kV or more Body charge (when the charge accumulated in the body is discharged over the sensor surface): 4kV or more Body charge differs between individuals. Sensor surface strength The sensor surface is covered with only a thin coating in order to acquire fingerprint information. Therefore, care should be taken when handling the sensor. Problems have been confirmed not to occur during the following tests. * Pressing 10,000 times with a finger (Pressing time: 2s/time) * Rubbing 10,000 times with a finger (Back and forth, 2s/time) * Scratching with a fingernail (20 times back and forth) * Rubbing strongly with a pencil (6H hardness) (20 times back and forth) * Rubbing with a tissue (1,000 times back and forth) Note that problems also occurred with the sensor surface during the following tests. * Pressing strongly with a needle (normal sewing needle) * Rubbing with an eraser * Rubbing with the tip of a ball point pen * Rubbing with steel wool
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CXA3271GE
Timing Chart
500ns
XSP (3F)
250ns
CLK (4C)
250ns 250ns
Strobe Point
480ns
Input level VIH = 0.7VDD VIL = 0.3VDD
Output level High 0.65VDD X 0.35VDD Low
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CXA3271GE
Input/output Signal
CK1 clock 2MHz Strobe point (CK Rise + 480ns)
CLK (4C) Input
F = 2.0MHz
500ns (1clk) 250ns
XSP (3F) Input 750ns 750ns
C_CK (4E) Output
500ns (1clk)
96.5s (193clk)
31.5s (63clk)
96.5s (193clk) 256 clk
31.5s (63clk)
RSRO (5F) Output
96s (192clk)
500ns (1clk)
500ns (1clk)
CSRO (5E) Output 16384s (32768clk) {(193 + 63) x (2 + 126)} 128s (256clk)
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CXA3271GE
250ns XSP (3F) Input
750ns
750ns
C_CK (4E) Output 500ns (1clk) 96.5s (193clk) 31.5s (63clk) 96.5s (193clk) 31.5s (63clk)
(Repeat 128 Times) AOUT (7E) Output 256.5s (513clk) ((192 + 1 + 63) x 2 + 1) 96s (192clk) 1st Culumn 32s (64clk) 96s 32s (192clk) (64clk) 2nd Culumn Analog output Air level 0.6 to 1.3V
2.0V AOUT (7E) Detail D-range average analog output 0.6V 500ns (1clk)
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CXA3271GE
Package Outline
Unit: mm
30PIN LLGA
0.2 M S A 17.58 0.25 (15.16) PIN1 INDEX
2.6 0.25
20 2.42 0.25
X
1.45 0.2 0.05MAX
0.2 M S B
(10.04)
4-R1.0MAX
12.64 0.25
17
0.2 0.2
Y SENSOR AREA 0.15
(0.85) S DETAIL X
52-1.2 0.08 3-2.2 G F E D C B A 12345 678 2.2 2.3 3.65 B 2.3 A 2.54 0.1 M S AB
0.25MAX TYP
0.25MAX TYP
2.54
DETAIL Y
2.07 2.2 2.07
3.42
NOTE1: Dimension "" does not include breedout of sensor area. NOTE2: The length of breedout is 0.25MAX.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LLGA-30P-01 ORGANIC SUBSTRATE TERMINAL TREATMENT GOLD PLATING TERMINAL MATERIAL PACKAGE MASS COPPER PLATING 0.7 g
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0.1 S
Sony Corporation

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